Simple rules

: IN : inputs
: BUFFER : outputs that never are tri-stated
: OUT : tri-statable outputs (unidirectional)
: INOUT : real bidirectional ports

More elaborate set of rules

VHDL’s features can help you if you let them. Here is a set of rules which we arrived at empirically, and which really work for us:

1) Any net that logically has a single driver should be declared, at all module levels in the hierarchy, as std_ulogic or std_ulogic_vector and the port type at the module interfaces should be IN or BUFFER.

2) Any net that logically has multiple drivers should be declared, at all driving module levels in the hierarchy, as std_logic or std_logic_vector and the port type at the module interfaces should be OUT or INOUT. If all of the drivers are limited to a single module (and perhaps its instantiated sub-modules), and the signal is to be exported from the module (toward the root of the hierarchy), then the signal should be cast/converted to a similarly-named std_ulogic or std_ulogic_vector and then exported through a BUFFER port. This rule can be ignored where external considerations (such as testbench requirements) require that the driven signal be std_logic or std_logic_vector.

3) In general, IN ports should use std_ulogic or std_ulogic_vector. This means that a cast/conversion from std_logic or std_logic_vector may be necessary in the instantiating hierarchy level. This rule can be ignored where it makes more sense to do the cast/conversion within the module, such as at the level of the chip pads.

4) Within library cells, all 2-state outputs where both states are actively driven (the norm) should be declared as BUFFERs. All 3-state outputs and single-ended outputs of library cells should be declared as OUTs. Within a chip, these rules lead to heavy use of BUFFERs and std_ulogic / std_ulogic_vector for normal nets. Tri-state nets and some nets with multiple single-ended drivers (fast carry logic and some dynamic logic come to mind) become the only internal std_logic / std_logic_vector nets.

Externally, the environment is not as well determined, and so external inputs to the chip can be declared either as std_logic or std_ulogic; this decision should be based on your standard project practice. Declaring the external signals as std_logic means that the inputs will need a conversion/cast at the point of logical pad-cell instantiation; declaring the external signals as std_ulogic is more consistent with the internal practice, facilitating reuse of the design as a macro, but may require cast/conversion in the testbench or board level of the hierarchy.

Many may disagree with these rules; no problem . But these rules do use the capabilities of VHDL for maximal early error detection — each std_ulogic net must have EXACTLY one driver. Also, in general the number of extra signals required for std_logic nets which have dual std_ulogic nets [because of the conversion/casts of (2) and (3)] will be less than the number of extra signals that will be required to provide output values within a module declared with OUTs. It took us quite a while to evolve this set of rules; they do work well.

Tom Phinney

Honeywell Inc.

Industrial Automation and Control

To size a number and store it in a std_logic_vector use the following:

assuming:

signal DataOut : std_logic_vector(0 to 31) ;

use:

DataOut <= std_logic_vector(to_unsigned(0,DataOut'length));