Archive for the FPGA Category

Pack:1239 Xilinx Warnings

Posted in FPGA on December 10, 2007 by aghoras

Sometimes during synthesis, XST spits out a warning saying something to the effect of “Can’t join a register to an input pin because they are not under the same hierarchy. Do one of the following to fix this problem: (three choices that flatten your design).”

I think this problem is caused by the synthesis tool trying to pack the edge registers into IOBs where it can’t get to certain signals. To fix this problem (and keep the design hierarchy) two things need to be done:

  1. Disable the Synthesis/Properties/Xilix Specifc Options/Pack I/O registers into IOBs. This can also be done on a module basis by using attributes like:
    attribute iob: string;
    attribute iob of lcl_control_regs_instance : label is "FALSE";
  2. Set Pack I/O Registers/Latches into IOBs to off under Map Properties